Advanced semiconductor chips, such as high performance microprocessor, microcontroller and communication chips, require high speed interconnect structures between individual semiconductor devices which are used to perform various functions such as logical operations, storing and retrieving data, providing control signals and the like. With the progress in the semiconductor device technology leading to ultra large scale integration, the overall speed of operation of the advanced semiconductor chips is approaching a limit due to signal propagation delay in interconnection wires, which are employed as the high speed interconnect structures, between the individual semiconductor devices on the same advanced semiconductor chip.
The signal propagation delay in an interconnect structure is dependent on an RC product of the interconnect structure, where R denotes the resistance of the interconnect wires and C denotes the interconnect capacitance, or the overall capacitance of the interconnect structure in which the interconnect wires are embedded. Use of copper instead of aluminum as the interconnect wiring material has allowed reduction of the resistance contribution to the RC product. Current focus in the microelectronics industry is on reducing the interconnect capacitance by employing low dielectric constant (low k) dielectric materials in the interconnect structure of the advanced semiconductor chips, which typically contain a multilayered interconnect structure.
Formation of an air gap within a dielectric layer has been proposed for reduction of an effective dielectric constant of the dielectric material layer in a back-end-of-line interconnect structure. Of particular relevance to the present invention is an air gap structure disclosed in U.S. Patent Application Publication No. 2005/0167838 to Edelstein et al., the entire contents of which are incorporated herein by reference. In this prior art, a self-assembling diblock copolymer resist is patterned over an interconnect structure and cavities of a sublithographic diameter are formed in a low dielectric constant (low-k) dielectric material layer. An isotropic etch is subsequently performed to merge multiple cavities of the sublithographic diameter to form a merged cavity in the dielectric material layer. Since the dielectric constant of air is substantially 1.0, the effective dielectric constant of the combination of the remaining dielectric layer and the merged cavity is less than the dielectric constant of the dielectric layer alone.
An inevitable consequence of this prior art method is generation of etch damage to exposed top surfaces of a metal line during the isotropic etch. Damages to the exposed top surfaces of the metal line by a reactive ion etch or a wet etch employing an etchant such as dilute hydrofluoric acid during the enlarging and merging of the cavities of a sublithographic diameter adversely impacts reliability characteristics of the interconnect structure.
When electrical current flows in the metal line, the metal ions are subjected to an electrostatic force due to the charge of the metal ion and the electric field to which the metal ion is exposed to. Further, as electrons scatter off the lattice during conduction of electrical current, the electrons transfer momentum to the metal ions in the lattice of the conductor material. The direction of the electrostatic force is in the direction of the electric field, i.e., in the direction of the current, and the direction of the force due to the momentum transfer of the electrons is in the direction of the flow of the electrons, i.e., in the opposite direction of the current. However, the force due to the momentum transfer of the electrons is in general greater than the electrostatic force. Thus, metal ions are subjected to a net force in the opposite direction of the current, or in the direction of the flow of the electrons.
High defect density, i.e., smaller grain size of the metal or high temperature typically increases electron scattering, and consequently, the amount of momentum transfer from the electrons to the conductor material. Such momentum transfer, if performed sufficiently cumulatively, may cause the metal ions to dislodge from the lattice and move physically. The mass transport caused by the electrical current, or the movement of the conductive material due to electrical current, is termed electromigration in the art. Electromigration may cause formation of a void in a metal line and/or in a metal via, and form an electric open in the metal line and/or in the metal via.
Thus, presence of physical defects, as is generated in the prior art interconnect structure of Edelstein et al., thus increases electron scattering during conduction of current, and degrades electromigration resistance of the metal line. Reliability of the prior art interconnect structure is undermined since formation of voids through electromigration is accelerated due to the presence of the defects formed on surfaces of a metal line during the merging of the sublithographic cavities.
In view of the above, there exists a need for an interconnect structure having an air gap in a low-k material layer without generating structural defects on surfaces of a metal line and methods of manufacturing the same.